GBDK 2020 Docs  4.4.0
API Documentation for GBDK 2020
Macros | Variables
hardware.h File Reference
#include <types.h>

Go to the source code of this file.

Macros

#define __BYTES   extern UBYTE
 
#define __BYTE_REG   extern volatile UBYTE
 
#define __REG   extern volatile SFR
 
#define MBC7_LATCH_ERASE   0x55u
 
#define MBC7_LATCH_CAPTURE   0xAAu
 
#define MBC7_SRAM_ENABLE_KEY_1   0x0Au
 
#define MBC7_SRAM_ENABLE_KEY_2   0x40u
 
#define rP1   P1_REG
 
#define P1F_5   0b00100000
 
#define P1F_4   0b00010000
 
#define P1F_3   0b00001000
 
#define P1F_2   0b00000100
 
#define P1F_1   0b00000010
 
#define P1F_0   0b00000001
 
#define P1F_GET_DPAD   P1F_5
 
#define P1F_GET_BTN   P1F_4
 
#define P1F_GET_NONE   (P1F_4 | P1F_5)
 
#define rSB   SB_REG
 
#define rSC   SC_REG
 
#define SIOF_XFER_START   0b10000000
 
#define SIOF_CLOCK_INT   0b00000001
 
#define SIOF_CLOCK_EXT   0b00000000
 
#define SIOF_SPEED_1X   0b00000000
 
#define SIOF_SPEED_32X   0b00000010
 
#define SIOF_B_CLOCK   0
 
#define SIOF_B_SPEED   1
 
#define SIOF_B_XFER_START   7
 
#define SCF_START   SIOF_XFER_START
 
#define SCF_SOURCE   SIOF_CLOCK_INT
 
#define SCF_SPEED   SIOF_SPEED_32X
 
#define rDIV   DIV_REG
 
#define rTIMA   TIMA_REG
 
#define rTMA   TMA_REG
 
#define rTAC   TAC_REG
 
#define TACF_START   0b00000100
 
#define TACF_STOP   0b00000000
 
#define TACF_4KHZ   0b00000000
 
#define TACF_16KHZ   0b00000011
 
#define TACF_65KHZ   0b00000010
 
#define TACF_262KHZ   0b00000001
 
#define rIF   IF_REG
 
#define rAUD1SWEEP   NR10_REG
 
#define AUD1SWEEP_UP   0b00000000
 
#define AUD1SWEEP_DOWN   0b00001000
 
#define AUD1SWEEP_TIME(x)   ((x) << 4)
 
#define AUD1SWEEP_LENGTH(x)   (x)
 
#define rAUD1LEN   NR11_REG
 
#define rAUD1ENV   NR12_REG
 
#define rAUD1LOW   NR13_REG
 
#define rAUD1HIGH   NR14_REG
 
#define rAUD2LEN   NR21_REG
 
#define rAUD2ENV   NR22_REG
 
#define rAUD2LOW   NR23_REG
 
#define rAUD2HIGH   NR24_REG
 
#define rAUD3ENA   NR30_REG
 
#define rAUD3LEN   NR31_REG
 
#define rAUD3LEVEL   NR32_REG
 
#define rAUD3LOW   NR33_REG
 
#define rAUD3HIGH   NR34_REG
 
#define rAUD4LEN   NR41_REG
 
#define rAUD4ENV   NR42_REG
 
#define rAUD4POLY   NR43_REG
 
#define AUD4POLY_WIDTH_15BIT   0x00
 
#define AUD4POLY_WIDTH_7BIT   0x08
 
#define rAUD4GO   NR44_REG
 
#define rAUDVOL   NR50_REG
 
#define AUDVOL_VOL_LEFT(x)   ((x) << 4)
 
#define AUDVOL_VOL_RIGHT(x)   ((x))
 
#define AUDVOL_VIN_LEFT   0b10000000
 
#define AUDVOL_VIN_RIGHT   0b00001000
 
#define rAUDTERM   NR51_REG
 
#define AUDTERM_4_LEFT   0b10000000
 
#define AUDTERM_3_LEFT   0b01000000
 
#define AUDTERM_2_LEFT   0b00100000
 
#define AUDTERM_1_LEFT   0b00010000
 
#define AUDTERM_4_RIGHT   0b00001000
 
#define AUDTERM_3_RIGHT   0b00000100
 
#define AUDTERM_2_RIGHT   0b00000010
 
#define AUDTERM_1_RIGHT   0b00000001
 
#define rAUDENA   NR52_REG
 
#define AUDENA_ON   0b10000000
 
#define AUDENA_OFF   0b00000000
 
#define rLCDC   LCDC_REG
 
#define LCDCF_OFF   0b00000000
 
#define LCDCF_ON   0b10000000
 
#define LCDCF_WIN9800   0b00000000
 
#define LCDCF_WIN9C00   0b01000000
 
#define LCDCF_WINOFF   0b00000000
 
#define LCDCF_WINON   0b00100000
 
#define LCDCF_BG8800   0b00000000
 
#define LCDCF_BG8000   0b00010000
 
#define LCDCF_BG9800   0b00000000
 
#define LCDCF_BG9C00   0b00001000
 
#define LCDCF_OBJ8   0b00000000
 
#define LCDCF_OBJ16   0b00000100
 
#define LCDCF_OBJOFF   0b00000000
 
#define LCDCF_OBJON   0b00000010
 
#define LCDCF_BGOFF   0b00000000
 
#define LCDCF_BGON   0b00000001
 
#define LCDCF_B_ON   7
 
#define LCDCF_B_WIN9C00   6
 
#define LCDCF_B_WINON   5
 
#define LCDCF_B_BG8000   4
 
#define LCDCF_B_BG9C00   3
 
#define LCDCF_B_OBJ16   2
 
#define LCDCF_B_OBJON   1
 
#define LCDCF_B_BGON   0
 
#define rSTAT   STAT_REG
 
#define STATF_LYC   0b01000000
 
#define STATF_MODE10   0b00100000
 
#define STATF_MODE01   0b00010000
 
#define STATF_MODE00   0b00001000
 
#define STATF_LYCF   0b00000100
 
#define STATF_HBL   0b00000000
 
#define STATF_VBL   0b00000001
 
#define STATF_OAM   0b00000010
 
#define STATF_LCD   0b00000011
 
#define STATF_BUSY   0b00000010
 
#define STATF_B_LYC   6
 
#define STATF_B_MODE10   5
 
#define STATF_B_MODE01   4
 
#define STATF_B_MODE00   3
 
#define STATF_B_LYCF   2
 
#define STATF_B_VBL   0
 
#define STATF_B_OAM   1
 
#define STATF_B_BUSY   1
 
#define rSCY
 
#define rSCX   SCX_REG
 
#define rLY   LY_REG
 
#define rLYC   LYC_REG
 
#define rDMA   DMA_REG
 
#define rBGP   BGP_REG
 
#define rOBP0   OBP0_REG
 
#define rOBP1   OBP1_REG
 
#define rWY   WY_REG
 
#define rWX   WX_REG
 
#define rKEY1   KEY1_REG
 
#define rSPD   KEY1_REG
 
#define KEY1F_DBLSPEED   0b10000000
 
#define KEY1F_PREPARE   0b00000001
 
#define rVBK   VBK_REG
 
#define VBK_BANK_0   0
 
#define VBK_TILES   0
 
#define VBK_BANK_1   1
 
#define VBK_ATTRIBUTES   1
 
#define BKGF_PRI   0b10000000
 
#define BKGF_YFLIP   0b01000000
 
#define BKGF_XFLIP   0b00100000
 
#define BKGF_BANK0   0b00000000
 
#define BKGF_BANK1   0b00001000
 
#define BKGF_CGB_PAL0   0b00000000
 
#define BKGF_CGB_PAL1   0b00000001
 
#define BKGF_CGB_PAL2   0b00000010
 
#define BKGF_CGB_PAL3   0b00000011
 
#define BKGF_CGB_PAL4   0b00000100
 
#define BKGF_CGB_PAL5   0b00000101
 
#define BKGF_CGB_PAL6   0b00000110
 
#define BKGF_CGB_PAL7   0b00000111
 
#define rHDMA1   HDMA1_REG
 
#define rHDMA2   HDMA2_REG
 
#define rHDMA3   HDMA3_REG
 
#define rHDMA4   HDMA4_REG
 
#define rHDMA5   HDMA5_REG
 
#define HDMA5F_MODE_GP   0b00000000
 
#define HDMA5F_MODE_HBL   0b10000000
 
#define HDMA5F_BUSY   0b10000000
 
#define rRP   RP_REG
 
#define RPF_ENREAD   0b11000000
 
#define RPF_DATAIN   0b00000010
 
#define RPF_WRITE_HI   0b00000001
 
#define RPF_WRITE_LO   0b00000000
 
#define rBCPS   BCPS_REG
 
#define BCPSF_AUTOINC   0b10000000
 
#define rBCPD   BCPD_REG
 
#define rOCPS   OCPS_REG
 
#define OCPSF_AUTOINC   0b10000000
 
#define rOCPD   OCPD_REG
 
#define rSVBK   SVBK_REG
 
#define rSMBK   SVBK_REG
 
#define rPCM12   PCM12_REG
 
#define rPCM34   PCM34_REG
 
#define rIE   IE_REG
 
#define IEF_HILO   0b00010000
 
#define IEF_SERIAL   0b00001000
 
#define IEF_TIMER   0b00000100
 
#define IEF_STAT   0b00000010
 
#define IEF_VBLANK   0b00000001
 
#define AUDLEN_DUTY_12_5   0b00000000
 
#define AUDLEN_DUTY_25   0b01000000
 
#define AUDLEN_DUTY_50   0b10000000
 
#define AUDLEN_DUTY_75   0b11000000
 
#define AUDLEN_LENGTH(x)   (x)
 
#define AUDENV_VOL(x)   ((x) << 4)
 
#define AUDENV_UP   0b00001000
 
#define AUDENV_DOWN   0b00000000
 
#define AUDENV_LENGTH(x)   (x)
 
#define AUDHIGH_RESTART   0b10000000
 
#define AUDHIGH_LENGTH_ON   0b01000000
 
#define AUDHIGH_LENGTH_OFF   0b00000000
 
#define OAMF_PRI   0b10000000
 
#define OAMF_YFLIP   0b01000000
 
#define OAMF_XFLIP   0b00100000
 
#define OAMF_PAL0   0b00000000
 
#define OAMF_PAL1   0b00010000
 
#define OAMF_BANK0   0b00000000
 
#define OAMF_BANK1   0b00001000
 
#define OAMF_CGB_PAL0   0b00000000
 
#define OAMF_CGB_PAL1   0b00000001
 
#define OAMF_CGB_PAL2   0b00000010
 
#define OAMF_CGB_PAL3   0b00000011
 
#define OAMF_CGB_PAL4   0b00000100
 
#define OAMF_CGB_PAL5   0b00000101
 
#define OAMF_CGB_PAL6   0b00000110
 
#define OAMF_CGB_PAL7   0b00000111
 
#define OAMF_PALMASK   0b00000111
 
#define DEVICE_SCREEN_X_OFFSET   0
 
#define DEVICE_SCREEN_Y_OFFSET   0
 
#define DEVICE_SCREEN_WIDTH   20
 
#define DEVICE_SCREEN_HEIGHT   18
 
#define DEVICE_SCREEN_BUFFER_WIDTH   32
 
#define DEVICE_SCREEN_BUFFER_HEIGHT   32
 
#define DEVICE_SCREEN_MAP_ENTRY_SIZE   1
 
#define DEVICE_SPRITE_PX_OFFSET_X   8
 
#define DEVICE_SPRITE_PX_OFFSET_Y   16
 
#define DEVICE_WINDOW_PX_OFFSET_X   7
 
#define DEVICE_WINDOW_PX_OFFSET_Y   0
 
#define DEVICE_SCREEN_PX_WIDTH   (DEVICE_SCREEN_WIDTH * 8)
 
#define DEVICE_SCREEN_PX_HEIGHT   (DEVICE_SCREEN_HEIGHT * 8)
 

Variables

__BYTES _VRAM []
 
__BYTES _VRAM8000 []
 
__BYTES _VRAM8800 []
 
__BYTES _VRAM9000 []
 
__BYTES _SCRN0 []
 
__BYTES _SCRN1 []
 
__BYTES _SRAM []
 
__BYTES _RAM []
 
__BYTES _RAMBANK []
 
__BYTES _OAMRAM []
 
__BYTE_REG _IO []
 
__BYTE_REG _AUD3WAVERAM []
 
__BYTE_REG _HRAM []
 
__BYTE_REG rRAMG
 
__BYTE_REG rROMB0
 
__BYTE_REG rROMB1
 
__BYTE_REG rRAMB
 
__BYTE_REG rMBC7_SRAM_ENABLE_1
 
__BYTE_REG rMBC7_SRAM_ENABLE_2
 
__BYTE_REG rMBC7_LATCH_1
 
__BYTE_REG rMBC7_LATCH_2
 
__BYTE_REG rMBC7_ACCEL_X_LO
 
__BYTE_REG rMBC7_ACCEL_X_HI
 
__BYTE_REG rMBC7_ACCEL_Y_LO
 
__BYTE_REG rMBC7_ACCEL_Y_HI
 
__REG P1_REG
 
__REG SB_REG
 
__REG SC_REG
 
__REG DIV_REG
 
__REG TIMA_REG
 
__REG TMA_REG
 
__REG TAC_REG
 
__REG IF_REG
 
__REG NR10_REG
 
__REG NR11_REG
 
__REG NR12_REG
 
__REG NR13_REG
 
__REG NR14_REG
 
__REG NR21_REG
 
__REG NR22_REG
 
__REG NR23_REG
 
__REG NR24_REG
 
__REG NR30_REG
 
__REG NR31_REG
 
__REG NR32_REG
 
__REG NR33_REG
 
__REG NR34_REG
 
__REG NR41_REG
 
__REG NR42_REG
 
__REG NR43_REG
 
__REG NR44_REG
 
__REG NR50_REG
 
__REG NR51_REG
 
__REG NR52_REG
 
__BYTE_REG AUD3WAVE [16]
 
__BYTE_REG PCM_SAMPLE [16]
 
__REG LCDC_REG
 
__REG STAT_REG
 
__REG SCY_REG
 
__REG SCX_REG
 
__REG LY_REG
 
__REG LYC_REG
 
__REG DMA_REG
 
__REG BGP_REG
 
__REG OBP0_REG
 
__REG OBP1_REG
 
__REG WY_REG
 
__REG WX_REG
 
__REG KEY1_REG
 
__REG VBK_REG
 
__REG HDMA1_REG
 
__REG HDMA2_REG
 
__REG HDMA3_REG
 
__REG HDMA4_REG
 
__REG HDMA5_REG
 
__REG RP_REG
 
__REG BCPS_REG
 
__REG BCPD_REG
 
__REG OCPS_REG
 
__REG OCPD_REG
 
__REG SVBK_REG
 
__REG PCM12_REG
 
__REG PCM34_REG
 
__REG IE_REG
 

Detailed Description

Defines that let the GB's hardware registers be accessed from C.

See the Pandocs for more details on each register.

Macro Definition Documentation

◆ __BYTES

#define __BYTES   extern UBYTE

◆ __BYTE_REG

#define __BYTE_REG   extern volatile UBYTE

◆ __REG

#define __REG   extern volatile SFR

◆ MBC7_LATCH_ERASE

#define MBC7_LATCH_ERASE   0x55u

◆ MBC7_LATCH_CAPTURE

#define MBC7_LATCH_CAPTURE   0xAAu

◆ MBC7_SRAM_ENABLE_KEY_1

#define MBC7_SRAM_ENABLE_KEY_1   0x0Au

◆ MBC7_SRAM_ENABLE_KEY_2

#define MBC7_SRAM_ENABLE_KEY_2   0x40u

◆ rP1

#define rP1   P1_REG

◆ P1F_5

#define P1F_5   0b00100000

◆ P1F_4

#define P1F_4   0b00010000

◆ P1F_3

#define P1F_3   0b00001000

◆ P1F_2

#define P1F_2   0b00000100

◆ P1F_1

#define P1F_1   0b00000010

◆ P1F_0

#define P1F_0   0b00000001

◆ P1F_GET_DPAD

#define P1F_GET_DPAD   P1F_5

◆ P1F_GET_BTN

#define P1F_GET_BTN   P1F_4

◆ P1F_GET_NONE

#define P1F_GET_NONE   (P1F_4 | P1F_5)

◆ rSB

#define rSB   SB_REG

◆ rSC

#define rSC   SC_REG

◆ SIOF_XFER_START

#define SIOF_XFER_START   0b10000000

Serial IO: Start Transfer. Automatically cleared at the end of transfer

◆ SIOF_CLOCK_INT

#define SIOF_CLOCK_INT   0b00000001

Serial IO: Use Internal clock

◆ SIOF_CLOCK_EXT

#define SIOF_CLOCK_EXT   0b00000000

Serial IO: Use External clock

◆ SIOF_SPEED_1X

#define SIOF_SPEED_1X   0b00000000

Serial IO: If internal clock then 8KHz mode, 1KB/s (16Khz in CGB high-speed mode, 2KB/s)

◆ SIOF_SPEED_32X

#define SIOF_SPEED_32X   0b00000010

Serial IO: CGB-Mode ONLY If internal clock then 256KHz mode, 32KB/s (512KHz in CGB high-speed mode, 64KB/s)

◆ SIOF_B_CLOCK

#define SIOF_B_CLOCK   0

◆ SIOF_B_SPEED

#define SIOF_B_SPEED   1

◆ SIOF_B_XFER_START

#define SIOF_B_XFER_START   7

◆ SCF_START

#define SCF_START   SIOF_XFER_START

◆ SCF_SOURCE

#define SCF_SOURCE   SIOF_CLOCK_INT

◆ SCF_SPEED

#define SCF_SPEED   SIOF_SPEED_32X

◆ rDIV

#define rDIV   DIV_REG

◆ rTIMA

#define rTIMA   TIMA_REG

◆ rTMA

#define rTMA   TMA_REG

◆ rTAC

#define rTAC   TAC_REG

◆ TACF_START

#define TACF_START   0b00000100

◆ TACF_STOP

#define TACF_STOP   0b00000000

◆ TACF_4KHZ

#define TACF_4KHZ   0b00000000

◆ TACF_16KHZ

#define TACF_16KHZ   0b00000011

◆ TACF_65KHZ

#define TACF_65KHZ   0b00000010

◆ TACF_262KHZ

#define TACF_262KHZ   0b00000001

◆ rIF

#define rIF   IF_REG

◆ rAUD1SWEEP

#define rAUD1SWEEP   NR10_REG

Sound Channel 1, NR10: Sweep

◆ AUD1SWEEP_UP

#define AUD1SWEEP_UP   0b00000000

For Sound Channel 1, NR10: Sweep Addition, period increases

◆ AUD1SWEEP_DOWN

#define AUD1SWEEP_DOWN   0b00001000

For Sound Channel 1, NR10: Sweep Subtraction, period decreases

◆ AUD1SWEEP_TIME

#define AUD1SWEEP_TIME (   x)    ((x) << 4)

For Sound Channel 1, NR10: Sweep Time/Pace, Range: 0-7

◆ AUD1SWEEP_LENGTH

#define AUD1SWEEP_LENGTH (   x)    (x)

For Sound Channel 1, NR10: Sweep Length/Individual step, Range: 0-7

◆ rAUD1LEN

#define rAUD1LEN   NR11_REG

Sound Channel 1, NR11: Sound length/Wave pattern duty

◆ rAUD1ENV

#define rAUD1ENV   NR12_REG

Sound Channel 1, NR12: Volume Envelope

◆ rAUD1LOW

#define rAUD1LOW   NR13_REG

Sound Channel 1, NR13: Frequency Low

◆ rAUD1HIGH

#define rAUD1HIGH   NR14_REG

Sound Channel 1, NR14: Frequency High

◆ rAUD2LEN

#define rAUD2LEN   NR21_REG

Sound Channel 2, NR21_REG: Tone

◆ rAUD2ENV

#define rAUD2ENV   NR22_REG

Sound Channel 2, NR22_REG: Volume Envelope

◆ rAUD2LOW

#define rAUD2LOW   NR23_REG

Sound Channel 2, NR23_REG: Frequency data Low

◆ rAUD2HIGH

#define rAUD2HIGH   NR24_REG

Sound Channel 2, NR24_REG: Frequency data High

◆ rAUD3ENA

#define rAUD3ENA   NR30_REG

Sound Channel 3, NR30_REG: Sound on/off

◆ rAUD3LEN

#define rAUD3LEN   NR31_REG

Sound Channel 3, NR31_REG: Sound Length

◆ rAUD3LEVEL

#define rAUD3LEVEL   NR32_REG

Sound Channel 3, NR32_REG: Select output level

◆ rAUD3LOW

#define rAUD3LOW   NR33_REG

Sound Channel 3, NR33_REG: Frequency data Low

◆ rAUD3HIGH

#define rAUD3HIGH   NR34_REG

Sound Channel 3, NR34_REG: Frequency data High

◆ rAUD4LEN

#define rAUD4LEN   NR41_REG

Sound Channel 4, NR41_REG: Sound Length

◆ rAUD4ENV

#define rAUD4ENV   NR42_REG

Sound Channel 4, NR42_REG: Volume Envelope

◆ rAUD4POLY

#define rAUD4POLY   NR43_REG

Sound Channel 4, NR43_REG: Polynomial Counter

◆ AUD4POLY_WIDTH_15BIT

#define AUD4POLY_WIDTH_15BIT   0x00

For Sound Channel 4, NR43_REG: Polynomial counter use 15 steps

◆ AUD4POLY_WIDTH_7BIT

#define AUD4POLY_WIDTH_7BIT   0x08

For Sound Channel 4, NR43_REG: Polynomial counter use 7 steps

◆ rAUD4GO

#define rAUD4GO   NR44_REG

Sound Channel 4, NR44_REG: Counter / Consecutive and Initial

◆ rAUDVOL

#define rAUDVOL   NR50_REG

Sound Master Volume, NR50: Volume and Cart external sound input (VIN)

◆ AUDVOL_VOL_LEFT

#define AUDVOL_VOL_LEFT (   x)    ((x) << 4)

For Sound Master Volume, NR50: Left Volume, Range: 0-7

◆ AUDVOL_VOL_RIGHT

#define AUDVOL_VOL_RIGHT (   x)    ((x))

For Sound Master Volume, NR50: Right Volume, Range: 0-7

◆ AUDVOL_VIN_LEFT

#define AUDVOL_VIN_LEFT   0b10000000

For Sound Master Volume, NR50: Cart external sound input (VIN) Left bit, 1 = ON, 0 = OFF

◆ AUDVOL_VIN_RIGHT

#define AUDVOL_VIN_RIGHT   0b00001000

For Sound Master Volume, NR50: Cart external sound input (VIN) Right bit, 1 = ON, 0 = OFF

◆ rAUDTERM

#define rAUDTERM   NR51_REG

Sound Panning, NR51: Enable/disable left and right output for sound channels

◆ AUDTERM_4_LEFT

#define AUDTERM_4_LEFT   0b10000000

For Sound Panning, NR51: Channel 4 Left bit, 1 = ON, 0 = OFF

◆ AUDTERM_3_LEFT

#define AUDTERM_3_LEFT   0b01000000

For Sound Panning, NR51: Channel 3 Left bit, 1 = ON, 0 = OFF

◆ AUDTERM_2_LEFT

#define AUDTERM_2_LEFT   0b00100000

For Sound Panning, NR51: Channel 2 Left bit, 1 = ON, 0 = OFF

◆ AUDTERM_1_LEFT

#define AUDTERM_1_LEFT   0b00010000

For Sound Panning, NR51: Channel 1 Left bit, 1 = ON, 0 = OFF

◆ AUDTERM_4_RIGHT

#define AUDTERM_4_RIGHT   0b00001000

For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF

◆ AUDTERM_3_RIGHT

#define AUDTERM_3_RIGHT   0b00000100

For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF

◆ AUDTERM_2_RIGHT

#define AUDTERM_2_RIGHT   0b00000010

For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF

◆ AUDTERM_1_RIGHT

#define AUDTERM_1_RIGHT   0b00000001

For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF

◆ rAUDENA

#define rAUDENA   NR52_REG

Sound Master Control, NR52: ON / OFF

◆ AUDENA_ON

#define AUDENA_ON   0b10000000

For Sound Master Control, NR52: Sound ON

◆ AUDENA_OFF

#define AUDENA_OFF   0b00000000

For Sound Master Control, NR52: Sound OFF

◆ rLCDC

#define rLCDC   LCDC_REG

◆ LCDCF_OFF

#define LCDCF_OFF   0b00000000

LCD Control: Off

◆ LCDCF_ON

#define LCDCF_ON   0b10000000

LCD Control: On

◆ LCDCF_WIN9800

#define LCDCF_WIN9800   0b00000000

Window Tile Map: Use 9800 Region

◆ LCDCF_WIN9C00

#define LCDCF_WIN9C00   0b01000000

Window Tile Map: Use 9C00 Region

◆ LCDCF_WINOFF

#define LCDCF_WINOFF   0b00000000

Window Display: Hidden

◆ LCDCF_WINON

#define LCDCF_WINON   0b00100000

Window Display: Visible

◆ LCDCF_BG8800

#define LCDCF_BG8800   0b00000000

BG & Window Tile Data: Use 8800 Region

◆ LCDCF_BG8000

#define LCDCF_BG8000   0b00010000

BG & Window Tile Data: Use 8000 Region

◆ LCDCF_BG9800

#define LCDCF_BG9800   0b00000000

BG Tile Map: use 9800 Region

◆ LCDCF_BG9C00

#define LCDCF_BG9C00   0b00001000

BG Tile Map: use 9C00 Region

◆ LCDCF_OBJ8

#define LCDCF_OBJ8   0b00000000

Sprites Size: 8x8 pixels

◆ LCDCF_OBJ16

#define LCDCF_OBJ16   0b00000100

Sprites Size: 8x16 pixels

◆ LCDCF_OBJOFF

#define LCDCF_OBJOFF   0b00000000

Sprites Display: Hidden

◆ LCDCF_OBJON

#define LCDCF_OBJON   0b00000010

Sprites Display: Visible

◆ LCDCF_BGOFF

#define LCDCF_BGOFF   0b00000000

Background Display: Hidden

◆ LCDCF_BGON

#define LCDCF_BGON   0b00000001

Background Display: Visible

◆ LCDCF_B_ON

#define LCDCF_B_ON   7

Bit for LCD On/Off Select

◆ LCDCF_B_WIN9C00

#define LCDCF_B_WIN9C00   6

Bit for Window Tile Map Region Select

◆ LCDCF_B_WINON

#define LCDCF_B_WINON   5

Bit for Window Display On/Off Control

◆ LCDCF_B_BG8000

#define LCDCF_B_BG8000   4

Bit for BG & Window Tile Data Region Select

◆ LCDCF_B_BG9C00

#define LCDCF_B_BG9C00   3

Bit for BG Tile Map Region Select

◆ LCDCF_B_OBJ16

#define LCDCF_B_OBJ16   2

Bit for Sprites Size Select

◆ LCDCF_B_OBJON

#define LCDCF_B_OBJON   1

Bit for Sprites Display Visible/Hidden Select

◆ LCDCF_B_BGON

#define LCDCF_B_BGON   0

Bit for Background Display Visible/Hidden Select

◆ rSTAT

#define rSTAT   STAT_REG

◆ STATF_LYC

#define STATF_LYC   0b01000000

STAT Interrupt: LYC=LY Coincidence Source Enable

◆ STATF_MODE10

#define STATF_MODE10   0b00100000

STAT Interrupt: Mode 2 OAM Source Enable

◆ STATF_MODE01

#define STATF_MODE01   0b00010000

STAT Interrupt: Mode 1 VBlank Source Enable

◆ STATF_MODE00

#define STATF_MODE00   0b00001000

STAT Interrupt: Mode 0 HBlank Source Enable

◆ STATF_LYCF

#define STATF_LYCF   0b00000100

LYC=LY Coincidence Status Flag, Set when LY contains the same value as LYC

◆ STATF_HBL

#define STATF_HBL   0b00000000

Current LCD Mode is: 0, in H-Blank

◆ STATF_VBL

#define STATF_VBL   0b00000001

Current LCD Mode is: 1, in V-Blank

◆ STATF_OAM

#define STATF_OAM   0b00000010

Current LCD Mode is: 2, in OAM-RAM is used by system (Searching OAM)

◆ STATF_LCD

#define STATF_LCD   0b00000011

Current LCD Mode is: 3, both OAM and VRAM used by system (Transferring Data to LCD Controller)

◆ STATF_BUSY

#define STATF_BUSY   0b00000010

When set, VRAM access is unsafe

◆ STATF_B_LYC

#define STATF_B_LYC   6

Bit for STAT Interrupt: LYC=LY Coincidence Source Enable

◆ STATF_B_MODE10

#define STATF_B_MODE10   5

Bit for STAT Interrupt: Mode 2 OAM Source Enable

◆ STATF_B_MODE01

#define STATF_B_MODE01   4

Bit for STAT Interrupt: Mode 1 VBlank Source Enable

◆ STATF_B_MODE00

#define STATF_B_MODE00   3

Bit for STAT Interrupt: Mode 0 HBlank Source Enable

◆ STATF_B_LYCF

#define STATF_B_LYCF   2

Bit for LYC=LY Coincidence Status Flag

◆ STATF_B_VBL

#define STATF_B_VBL   0

◆ STATF_B_OAM

#define STATF_B_OAM   1

◆ STATF_B_BUSY

#define STATF_B_BUSY   1

Bit for when VRAM access is unsafe

◆ rSCY

#define rSCY

◆ rSCX

#define rSCX   SCX_REG

◆ rLY

#define rLY   LY_REG

◆ rLYC

#define rLYC   LYC_REG

◆ rDMA

#define rDMA   DMA_REG

◆ rBGP

#define rBGP   BGP_REG

◆ rOBP0

#define rOBP0   OBP0_REG

◆ rOBP1

#define rOBP1   OBP1_REG

◆ rWY

#define rWY   WY_REG

◆ rWX

#define rWX   WX_REG

◆ rKEY1

#define rKEY1   KEY1_REG

◆ rSPD

#define rSPD   KEY1_REG

◆ KEY1F_DBLSPEED

#define KEY1F_DBLSPEED   0b10000000

◆ KEY1F_PREPARE

#define KEY1F_PREPARE   0b00000001

◆ rVBK

#define rVBK   VBK_REG

◆ VBK_BANK_0

#define VBK_BANK_0   0

Select Regular Map and Normal Tiles (CGB Mode Only)

◆ VBK_TILES

#define VBK_TILES   0

Select Regular Map and Normal Tiles (CGB Mode Only)

◆ VBK_BANK_1

#define VBK_BANK_1   1

Select Map Attributes and Extra Tile Bank (CGB Mode Only)

◆ VBK_ATTRIBUTES

#define VBK_ATTRIBUTES   1

Select Map Attributes and Extra Tile Bank (CGB Mode Only)

◆ BKGF_PRI

#define BKGF_PRI   0b10000000

Background CGB BG and Window over Sprite priority Enabled

◆ BKGF_YFLIP

#define BKGF_YFLIP   0b01000000

Background CGB Y axis flip: Vertically mirrored

◆ BKGF_XFLIP

#define BKGF_XFLIP   0b00100000

Background CGB X axis flip: Horizontally mirrored

◆ BKGF_BANK0

#define BKGF_BANK0   0b00000000

Background CGB Tile VRAM-Bank: Use Bank 0 (CGB Mode Only)

◆ BKGF_BANK1

#define BKGF_BANK1   0b00001000

Background CGB Tile VRAM-Bank: Use Bank 1 (CGB Mode Only)

◆ BKGF_CGB_PAL0

#define BKGF_CGB_PAL0   0b00000000

Background CGB Palette number (CGB Mode Only)

◆ BKGF_CGB_PAL1

#define BKGF_CGB_PAL1   0b00000001

Background CGB Palette number (CGB Mode Only)

◆ BKGF_CGB_PAL2

#define BKGF_CGB_PAL2   0b00000010

Background CGB Palette number (CGB Mode Only)

◆ BKGF_CGB_PAL3

#define BKGF_CGB_PAL3   0b00000011

Background CGB Palette number (CGB Mode Only)

◆ BKGF_CGB_PAL4

#define BKGF_CGB_PAL4   0b00000100

Background CGB Palette number (CGB Mode Only)

◆ BKGF_CGB_PAL5

#define BKGF_CGB_PAL5   0b00000101

Background CGB Palette number (CGB Mode Only)

◆ BKGF_CGB_PAL6

#define BKGF_CGB_PAL6   0b00000110

Background CGB Palette number (CGB Mode Only)

◆ BKGF_CGB_PAL7

#define BKGF_CGB_PAL7   0b00000111

Background CGB Palette number (CGB Mode Only)

◆ rHDMA1

#define rHDMA1   HDMA1_REG

◆ rHDMA2

#define rHDMA2   HDMA2_REG

◆ rHDMA3

#define rHDMA3   HDMA3_REG

◆ rHDMA4

#define rHDMA4   HDMA4_REG

◆ rHDMA5

#define rHDMA5   HDMA5_REG

◆ HDMA5F_MODE_GP

#define HDMA5F_MODE_GP   0b00000000

◆ HDMA5F_MODE_HBL

#define HDMA5F_MODE_HBL   0b10000000

◆ HDMA5F_BUSY

#define HDMA5F_BUSY   0b10000000

◆ rRP

#define rRP   RP_REG

◆ RPF_ENREAD

#define RPF_ENREAD   0b11000000

◆ RPF_DATAIN

#define RPF_DATAIN   0b00000010

◆ RPF_WRITE_HI

#define RPF_WRITE_HI   0b00000001

◆ RPF_WRITE_LO

#define RPF_WRITE_LO   0b00000000

◆ rBCPS

#define rBCPS   BCPS_REG

◆ BCPSF_AUTOINC

#define BCPSF_AUTOINC   0b10000000

◆ rBCPD

#define rBCPD   BCPD_REG

◆ rOCPS

#define rOCPS   OCPS_REG

◆ OCPSF_AUTOINC

#define OCPSF_AUTOINC   0b10000000

◆ rOCPD

#define rOCPD   OCPD_REG

◆ rSVBK

#define rSVBK   SVBK_REG

◆ rSMBK

#define rSMBK   SVBK_REG

◆ rPCM12

#define rPCM12   PCM12_REG

◆ rPCM34

#define rPCM34   PCM34_REG

◆ rIE

#define rIE   IE_REG

◆ IEF_HILO

#define IEF_HILO   0b00010000

Joypad interrupt enable flag

◆ IEF_SERIAL

#define IEF_SERIAL   0b00001000

Serial interrupt enable flag

◆ IEF_TIMER

#define IEF_TIMER   0b00000100

Timer interrupt enable flag

◆ IEF_STAT

#define IEF_STAT   0b00000010

Stat interrupt enable flag

◆ IEF_VBLANK

#define IEF_VBLANK   0b00000001

VBlank interrupt enable flag

◆ AUDLEN_DUTY_12_5

#define AUDLEN_DUTY_12_5   0b00000000

◆ AUDLEN_DUTY_25

#define AUDLEN_DUTY_25   0b01000000

◆ AUDLEN_DUTY_50

#define AUDLEN_DUTY_50   0b10000000

◆ AUDLEN_DUTY_75

#define AUDLEN_DUTY_75   0b11000000

◆ AUDLEN_LENGTH

#define AUDLEN_LENGTH (   x)    (x)

◆ AUDENV_VOL

#define AUDENV_VOL (   x)    ((x) << 4)

◆ AUDENV_UP

#define AUDENV_UP   0b00001000

◆ AUDENV_DOWN

#define AUDENV_DOWN   0b00000000

◆ AUDENV_LENGTH

#define AUDENV_LENGTH (   x)    (x)

◆ AUDHIGH_RESTART

#define AUDHIGH_RESTART   0b10000000

◆ AUDHIGH_LENGTH_ON

#define AUDHIGH_LENGTH_ON   0b01000000

◆ AUDHIGH_LENGTH_OFF

#define AUDHIGH_LENGTH_OFF   0b00000000

◆ OAMF_PRI

#define OAMF_PRI   0b10000000

BG and Window over Sprite Enabled

◆ OAMF_YFLIP

#define OAMF_YFLIP   0b01000000

Sprite Y axis flip: Vertically mirrored

◆ OAMF_XFLIP

#define OAMF_XFLIP   0b00100000

Sprite X axis flip: Horizontally mirrored

◆ OAMF_PAL0

#define OAMF_PAL0   0b00000000

Sprite Palette number: use OBP0 (Non-CGB Mode Only)

◆ OAMF_PAL1

#define OAMF_PAL1   0b00010000

Sprite Palette number: use OBP1 (Non-CGB Mode Only)

◆ OAMF_BANK0

#define OAMF_BANK0   0b00000000

Sprite Tile VRAM-Bank: Use Bank 0 (CGB Mode Only)

◆ OAMF_BANK1

#define OAMF_BANK1   0b00001000

Sprite Tile VRAM-Bank: Use Bank 1 (CGB Mode Only)

◆ OAMF_CGB_PAL0

#define OAMF_CGB_PAL0   0b00000000

Sprite CGB Palette number: use OCP0 (CGB Mode Only)

◆ OAMF_CGB_PAL1

#define OAMF_CGB_PAL1   0b00000001

Sprite CGB Palette number: use OCP1 (CGB Mode Only)

◆ OAMF_CGB_PAL2

#define OAMF_CGB_PAL2   0b00000010

Sprite CGB Palette number: use OCP2 (CGB Mode Only)

◆ OAMF_CGB_PAL3

#define OAMF_CGB_PAL3   0b00000011

Sprite CGB Palette number: use OCP3 (CGB Mode Only)

◆ OAMF_CGB_PAL4

#define OAMF_CGB_PAL4   0b00000100

Sprite CGB Palette number: use OCP4 (CGB Mode Only)

◆ OAMF_CGB_PAL5

#define OAMF_CGB_PAL5   0b00000101

Sprite CGB Palette number: use OCP5 (CGB Mode Only)

◆ OAMF_CGB_PAL6

#define OAMF_CGB_PAL6   0b00000110

Sprite CGB Palette number: use OCP6 (CGB Mode Only)

◆ OAMF_CGB_PAL7

#define OAMF_CGB_PAL7   0b00000111

Sprite CGB Palette number: use OCP7 (CGB Mode Only)

◆ OAMF_PALMASK

#define OAMF_PALMASK   0b00000111

Mask for Sprite CGB Palette number (CGB Mode Only)

◆ DEVICE_SCREEN_X_OFFSET

#define DEVICE_SCREEN_X_OFFSET   0

Offset of visible screen (in tile units) from left edge of hardware map

◆ DEVICE_SCREEN_Y_OFFSET

#define DEVICE_SCREEN_Y_OFFSET   0

Offset of visible screen (in tile units) from top edge of hardware map

◆ DEVICE_SCREEN_WIDTH

#define DEVICE_SCREEN_WIDTH   20

Width of visible screen in tile units

◆ DEVICE_SCREEN_HEIGHT

#define DEVICE_SCREEN_HEIGHT   18

Height of visible screen in tile units

◆ DEVICE_SCREEN_BUFFER_WIDTH

#define DEVICE_SCREEN_BUFFER_WIDTH   32

Width of hardware map buffer in tile units

◆ DEVICE_SCREEN_BUFFER_HEIGHT

#define DEVICE_SCREEN_BUFFER_HEIGHT   32

Height of hardware map buffer in tile units

◆ DEVICE_SCREEN_MAP_ENTRY_SIZE

#define DEVICE_SCREEN_MAP_ENTRY_SIZE   1

Number of bytes per hardware map entry

◆ DEVICE_SPRITE_PX_OFFSET_X

#define DEVICE_SPRITE_PX_OFFSET_X   8

Offset of sprite X coordinate origin (in pixels) from left edge of visible screen

◆ DEVICE_SPRITE_PX_OFFSET_Y

#define DEVICE_SPRITE_PX_OFFSET_Y   16

Offset of sprite Y coordinate origin (in pixels) from top edge of visible screen

◆ DEVICE_WINDOW_PX_OFFSET_X

#define DEVICE_WINDOW_PX_OFFSET_X   7

Minimal X coordinate of the window layer

◆ DEVICE_WINDOW_PX_OFFSET_Y

#define DEVICE_WINDOW_PX_OFFSET_Y   0

Minimal Y coordinate of the window layer

◆ DEVICE_SCREEN_PX_WIDTH

#define DEVICE_SCREEN_PX_WIDTH   (DEVICE_SCREEN_WIDTH * 8)

Width of visible screen in pixels

◆ DEVICE_SCREEN_PX_HEIGHT

#define DEVICE_SCREEN_PX_HEIGHT   (DEVICE_SCREEN_HEIGHT * 8)

Height of visible screen in pixels

Variable Documentation

◆ _VRAM

__BYTES _VRAM[]

Memory map

◆ _VRAM8000

__BYTES _VRAM8000[]

◆ _VRAM8800

__BYTES _VRAM8800[]

◆ _VRAM9000

__BYTES _VRAM9000[]

◆ _SCRN0

__BYTES _SCRN0[]

◆ _SCRN1

__BYTES _SCRN1[]

◆ _SRAM

__BYTES _SRAM[]

◆ _RAM

__BYTES _RAM[]

◆ _RAMBANK

__BYTES _RAMBANK[]

◆ _OAMRAM

__BYTES _OAMRAM[]

◆ _IO

__BYTE_REG _IO[]

◆ _AUD3WAVERAM

__BYTE_REG _AUD3WAVERAM[]

◆ _HRAM

__BYTE_REG _HRAM[]

◆ rRAMG

__BYTE_REG rRAMG

MBC5 registers

◆ rROMB0

__BYTE_REG rROMB0

◆ rROMB1

__BYTE_REG rROMB1

◆ rRAMB

__BYTE_REG rRAMB

◆ rMBC7_SRAM_ENABLE_1

__BYTE_REG rMBC7_SRAM_ENABLE_1

MBC7 registers

◆ rMBC7_SRAM_ENABLE_2

__BYTE_REG rMBC7_SRAM_ENABLE_2

◆ rMBC7_LATCH_1

__BYTE_REG rMBC7_LATCH_1

◆ rMBC7_LATCH_2

__BYTE_REG rMBC7_LATCH_2

◆ rMBC7_ACCEL_X_LO

__BYTE_REG rMBC7_ACCEL_X_LO

◆ rMBC7_ACCEL_X_HI

__BYTE_REG rMBC7_ACCEL_X_HI

◆ rMBC7_ACCEL_Y_LO

__BYTE_REG rMBC7_ACCEL_Y_LO

◆ rMBC7_ACCEL_Y_HI

__BYTE_REG rMBC7_ACCEL_Y_HI

◆ P1_REG

__REG P1_REG

IO Registers Joystick register

See also
joypad(), add_JOY(), IEF_HILO, P1F_5, P1F_4, P1F_3, P1F_2, P1F_1, P1F_0, P1F_GET_DPAD, P1F_GET_BTN, P1F_GET_NONE

◆ SB_REG

__REG SB_REG

Serial IO data buffer

◆ SC_REG

__REG SC_REG

Serial IO control register

◆ DIV_REG

__REG DIV_REG

Divider register

◆ TIMA_REG

__REG TIMA_REG

Timer counter

◆ TMA_REG

__REG TMA_REG

Timer modulo

◆ TAC_REG

__REG TAC_REG

Timer control

◆ IF_REG

__REG IF_REG

Interrupt flags: IEF_HILO, IEF_SERIAL, IEF_TIMER, IEF_STAT, IEF_VBLANK

◆ NR10_REG

__REG NR10_REG

Sound Channel 1, NR10: Sweep

◆ NR11_REG

__REG NR11_REG

Sound Channel 1, NR11: Sound length/Wave pattern duty

◆ NR12_REG

__REG NR12_REG

Sound Channel 1, NR12: Volume Envelope

◆ NR13_REG

__REG NR13_REG

Sound Channel 1, NR13: Frequency Low

◆ NR14_REG

__REG NR14_REG

Sound Channel 1, NR14: Frequency High

◆ NR21_REG

__REG NR21_REG

Sound Channel 2, NR21_REG: Tone

◆ NR22_REG

__REG NR22_REG

Sound Channel 2, NR22_REG: Volume Envelope

◆ NR23_REG

__REG NR23_REG

Sound Channel 2, NR23_REG: Frequency data Low

◆ NR24_REG

__REG NR24_REG

Sound Channel 2, NR24_REG: Frequency data High

◆ NR30_REG

__REG NR30_REG

Sound Channel 3, NR30_REG: Sound on/off

◆ NR31_REG

__REG NR31_REG

Sound Channel 3, NR31_REG: Sound Length

◆ NR32_REG

__REG NR32_REG

Sound Channel 3, NR32_REG: Select output level

◆ NR33_REG

__REG NR33_REG

Sound Channel 3, NR33_REG: Frequency data Low

◆ NR34_REG

__REG NR34_REG

Sound Channel 3, NR34_REG: Frequency data High

◆ NR41_REG

__REG NR41_REG

Sound Channel 4, NR41_REG: Sound Length

◆ NR42_REG

__REG NR42_REG

Sound Channel 4, NR42_REG: Volume Envelope

◆ NR43_REG

__REG NR43_REG

Sound Channel 4, NR43_REG: Polynomial Counter

◆ NR44_REG

__REG NR44_REG

Sound Channel 4, NR44_REG: Counter / Consecutive and Initial

◆ NR50_REG

__REG NR50_REG

Sound Master Volume, NR50: Volume and Cart external sound input (VIN)

◆ NR51_REG

__REG NR51_REG

Sound Panning, NR51: Enable/disable left and right output for sound channels

◆ NR52_REG

__REG NR52_REG

Sound Master Control, NR52: ON / OFF

◆ AUD3WAVE

__BYTE_REG AUD3WAVE[16]

◆ PCM_SAMPLE

__BYTE_REG PCM_SAMPLE[16]

◆ LCDC_REG

__REG LCDC_REG

LCD control

◆ STAT_REG

__REG STAT_REG

LCD status

◆ SCY_REG

__REG SCY_REG

Scroll Y

◆ SCX_REG

__REG SCX_REG

Scroll X

◆ LY_REG

__REG LY_REG

LCDC Y-coordinate

◆ LYC_REG

__REG LYC_REG

LY compare

◆ DMA_REG

__REG DMA_REG

DMA transfer

◆ BGP_REG

__REG BGP_REG

Set and Read the Background palette.

Example with the DMG_PALETTE() helper function and constants:
BGP_REG = DMG_PALETTE(DMG_BLACK, DMG_DARK_GRAY, DMG_LITE_GRAY, DMG_WHITE);

◆ OBP0_REG

__REG OBP0_REG

Set and Read the OBJ (Sprite) palette 0.

The first color entry is always transparent.

Example with the DMG_PALETTE() helper function and constants:
OBP0_REG = DMG_PALETTE(DMG_BLACK, DMG_DARK_GRAY, DMG_LITE_GRAY, DMG_WHITE);

◆ OBP1_REG

__REG OBP1_REG

Set and Read the OBJ (Sprite) palette 1.

The first color entry is always transparent.

Example with the DMG_PALETTE() helper function and constants:
OBP1_REG = DMG_PALETTE(DMG_BLACK, DMG_DARK_GRAY, DMG_LITE_GRAY, DMG_WHITE);

◆ WY_REG

__REG WY_REG

Window Y coordinate

◆ WX_REG

__REG WX_REG

Window X coordinate

◆ KEY1_REG

__REG KEY1_REG

CPU speed

◆ VBK_REG

__REG VBK_REG

VRAM bank select (CGB only)

See also
VBK_BANK_0, VBK_TILES, VBK_BANK_1, VBK_ATTRIBUTES

◆ HDMA1_REG

__REG HDMA1_REG

DMA control 1

◆ HDMA2_REG

__REG HDMA2_REG

DMA control 2

◆ HDMA3_REG

__REG HDMA3_REG

DMA control 3

◆ HDMA4_REG

__REG HDMA4_REG

DMA control 4

◆ HDMA5_REG

__REG HDMA5_REG

DMA control 5

◆ RP_REG

__REG RP_REG

IR port

◆ BCPS_REG

__REG BCPS_REG

BG color palette specification

◆ BCPD_REG

__REG BCPD_REG

BG color palette data

◆ OCPS_REG

__REG OCPS_REG

OBJ color palette specification

◆ OCPD_REG

__REG OCPD_REG

OBJ color palette data

◆ SVBK_REG

__REG SVBK_REG

Selects the WRAM upper region bank (CGB Only). WRAM Banking is NOT officially supported in GBDK and SDCC. The stack must be moved and other special care taken.

◆ PCM12_REG

__REG PCM12_REG

Sound channel 1&2 PCM amplitude (R)

◆ PCM34_REG

__REG PCM34_REG

Sound channel 3&4 PCM amplitude (R)

◆ IE_REG

__REG IE_REG

Interrupt enable